1. Field of the Invention
The present invention relates to a liquid crystal display control device which is used to reduce the storage capacity of a storage element required when an image formed from video signals transmitted from a personal computer or the like is displayed in an enlarged mode on a liquid crystal display device.
2. Description of Related Art
A technique as disclosed in Japanese Laid-open Patent Application No. Hei-4-12393 has been known as a liquid crystal display control device for displaying video information from a personal computer or the like while enlarging the video information. In this technique, a video signal transmitted from a personal computer or the like is temporarily stored in a frame memory, and the stored data are read out at a timing which is compatible with a liquid crystal display operation. This technique will be described in detail with reference to FIGS. 12 and 13.
FIG. 12 is a block diagram showing a control circuit in a liquid crystal display device disclosed in Japanese Laid-open Patent Application No. Hei-4-12393. In FIG. 12, reference numeral 1101 represents a video signal from a personal computer or the like, and reference numeral 1102 represents a synchronous signal. Reference numeral 1103 represents a horizontal/vertical timing and basic clock generating circuit, reference numeral 1104 represents an automatic input signal discriminant circuit, reference numeral 1105 represents a frame memory data generating and frame memory write-in circuit, reference numeral 1106 represents a frame memory circuit which comprises a field memory and a line buffer, reference numeral 1107 represents a frame memory read-out and display data generating circuit, reference numeral 1108 represents an enlarged display control circuit, reference numeral 1109 represents a liquid crystal display circuit, and reference numeral 1110 represents a liquid crystal display unit.
FIG. 13 is a block diagram showing the details of the frame memory circuit 1106 shown in FIG. 12. In FIG. 13, reference numeral 1201 represents a field memory, reference numeral 1202 represents a line buffer and reference numeral 1203 represents a read-out data select circuit.
In FIGS. 12 and 13, the horizontal/vertical timing and basic clock generating circuit 1103 generates a horizontal timing signal, a vertical timing signal and a basic clock signal CK1 for controlling the operation of the frame memory data generating and frame memory write-in circuit 1105 on the basis of the horizontal and vertical synchronous signals 1102 for driving a CRT display device which are input from the personal computer or the like.
The frame memory data generating and frame memory write-in circuit 1105 generates a control signal WRCT (write clock signal SWCK, write enable signal WE, reset write signal RSTW) on the basis of the basic clock signal CK1, and outputs the control signal WRCT to the field memory 1201 (see FIG. 13). Further, using the frame memory data generating and frame memory write-in circuit 1105, memory data Din of one frame which are generated on the basis of the video signal 1101 input from the personal computer or the like are successively written and temporarily stored into the field memory 1201.
Furthermore, the frame memory read-out and display data generating circuit 1107 generates a control signal RDCT on the basis of the clock signal CK2 for driving the liquid crystal display, generated by the liquid crystal display circuit 1109, and the control signal generated by the enlarged display control circuit 1108, and then outputs the control signal RDCT to the frame memory circuit 1106. The clock signal CK2 for driving the liquid crystal display is set to have a longer period than the basic clock signal CK1.
The control signal RDCT comprises a read clock signal SRCK, a read reset signal RSTR, a write clock signal WCK, a reset write signal RSTWN, a read clock signal RCK, a reset read signal RSTRN and a data selection signal SELDT. Of these signals, the read clock signal SRCK and the read reset signal RSTR are supplied to the field memory 1201. The write clock signal WCK, the reset write signal RSTWN, the read clock signal RCK and the reset read signal RSTRN are supplied to the line buffer 1202 of the frame memory circuit 1106. The data selection signal SELDT is supplied to the read-out data select circuit 1203 of the frame memory 1106.
The read-out data select circuit 1203 selects any one of an output data D1 of the field memory 1201 and an output data D2 of the line buffer 1202, and outputs the selected data as frame memory read-out data Dout.
On the basis of the data Dout, the frame memory read-out and display data generating circuit 1107 as described above generates serial liquid crystal display data which are compatible with the liquid crystal display unit 1110.
On the basis of the clock signal CK2 for driving the liquid crystal display, the liquid crystal display circuit 1109 generates a liquid crystal display driving signal, a data shift clock signal and an alternating signal which are compatible with the format of the liquid crystal display unit 1110.
The liquid crystal display unit 1110 displays a predetermined image on the basis of the liquid crystal display data output from the frame memory read-out and display data generating circuit 1107 and the signal output from the liquid crystal display circuit 1109.
The enlarged display control circuit 1108 judges whether an instruction for enlarging a part of the frame is made by an operator. If it is judged that the enlarge display instruction is made, the enlarged display control circuit 1108 controls the frame memory data generating and frame memory write-in circuit 1105 and the frame memory read-out and display data generating circuit 1107 in accordance with information on an indicated magnification rate, an enlarging area, etc.
Further, the automatic input signal discriminant circuit 1104 discriminates, on the basis of the synchronous signal 1102, an input video signal which is varied in accordance with, for example, the type of personal computer, and it controls the horizontal/vertical timing and basic clock generating circuit 1103 in accordance with the discrimination result.
According to the above-described technique, the enlargement processing can be performed. However, since the input and output operations of the video signals are perfectly asynchronously controlled by using a field memory, the field memory must have a storage capacity for storing video information of at least one frame. The memory capacity in which the video information of one frame can be stored is not so small in the present memory technique.
Furthermore, in the conventional technique as described above, all video signals are temporarily stored in the frame memory circuit 1106 so as to keep the read-out timing to the liquid crystal display unit constant at all times. Therefore, when a high-resolution video signal is input, a field memory to which high-speed access can be made is required irrespective of use and non-use of the enlargement processing. The use of a memory which can be accessed at high speed is a factor preventing cost reduction of the display device, because such a memory is expensive.